AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 69

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

update the status of the current (first) TDTE with the
BUFF and UFLO bits being set. If DXSUFLO is 0 (bit 6
CSR3), then this will cause the transmitter to be dis-
abled (CSR0, TXON = 0). The PCnet-ISA II controller
will have to be restarted to restore the transmit function.
The situation that matches this description implies that
the system has not been able to stay ahead of the PC-
net-ISA II controller in the transmit descriptor ring and
therefore, the condition is treated as a fatal error. To
avoid this situation, the system should always set the
transmit chain descriptor own bits in reverse order.
If the PCnet-ISA II controller does own the second
TDTE in a chain, it will gradually empty the contents of
the first buffer (as the bytes are needed by the transmit
operation), perform a single-cycle DMA transfer to
update the status (reset the OWN bit in TMD1) of the
first descriptor, and then it may perform one data DMA
access on the second buffer in the chain before execut-
ing another lookahead operation. (i.e. a lookahead to
the third descriptor).
The PCnet-ISA II controller can queue up to two pack-
ets in the transmit FIFO. Call them packet “X” and
packet “Y”, where “Y” is after “X”. Assume that packet
“X” is currently being transmitted. Because the PC-
net-ISA II controller can perform lookahead data trans-
fer over an ENP, it is possible for the PCnet-ISA II
controller to update a TDTE in a buffer belonging to
packet “Y” while packet “X” is being transmitted if
packet “Y” uses data chaining. This operation will result
in non-sequential TDTE accesses as packet “X” com-
pletes transmission and the PCnet-ISA II controller
writes out its status, since packet “X”’s TDTE is before
the TDTE accessed as part of the lookahead data
transfer from packet “Y”.
This should not cause any problem for properly written
software which processes buffers in sequence, waiting
for ownership before proceeding.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, then
TMD2 and TMD1 of the current buffer will be written; in
that case, data transfers from the next buffer will not
commence. Instead, following the TMD2/TMD1 up-
date, the PCnet-ISA II controller will go to the next
transmit packet, if any, skipping over the rest of the
packet which experienced an error, including chained
buffers.
This is done by returning to the polling microcode
where it will immediately access the next descriptor
and find the condition OWN = 1 and STP = 0 as
described earlier. In that case, the PCnet-ISA II control-
ler will reset the own bit for this descriptor and continue
in like manner until a descriptor with OWN = 0 (no more
transmit packets in the ring) or OWN = 1 and STP = 1
(the first buffer of a new packet) is reached.
Am79C961A
At the end of any transmit operation, whether success-
ful or with errors, and the completion of the descriptor
updates, the PCnet-ISA II controller will always perform
another poll operation. As described earlier, this poll
operation will begin with a check of the current RDTE,
unless the PCnet-ISA II controller already owns that
descriptor. Then the PCnet-ISA II controller will
proceed to polling the next TDTE. If the transmit
descriptor OWN bit has a zero value, then the PC-
net-ISA II controller will resume poll time count
incrementation. If the transmit descriptor OWN bit has
a value of ONE, then the PCnet-ISA II controller will
begin filling the FIFO with transmit data and initiate a
transmission. This end-of-operation poll avoids insert-
ing poll time counts between successive transmit
packets.
Whenever the PCnet-ISA II controller completes a
transmit packet (either with or without error) and writes
the status information to the current descriptor, then the
TINT bit of CSR0 is set to indicate the completion of a
transmission. This causes an interrupt signal if the
IENA bit of CSR0 has been set and the TINTM bit of
CSR3 is reset.
Receive Descriptor Table Entry (RDTE)
If the PCnet-ISA II controller does not own both the cur-
rent and the next Receive Descriptor Table Entry, then
the PCnet-ISA II controller will continue to poll accord-
ing to the polling sequence described above. If the
receive descriptor ring length is 1, there is no next
descriptor, and no look ahead poll will take place.
If a poll operation has revealed that the current and the
next RDTE belongs to the PCnet-ISA II controller, then
additional poll accesses are not necessary. Future poll
operations will not include RDTE accesses as long as
the PCnet-ISA II controller retains ownership to the cur-
rent and the next RDTE.
When receive activity is present on the channel, the
PCnet-ISA II controller waits for the complete address
of the message to arrive. It then decides whether to
accept or reject the packet based on all active address-
ing schemes. If the packet is accepted the PCnet-ISA II
controller checks the current receive buffer status reg-
ister CRST (CSR40) to determine the ownership of the
current buffer.
If ownership is lacking, then the PCnet-ISA II controller
will immediately perform a (last ditch) poll of the current
RDTE. If ownership is still denied, then the PCnet-ISA
II controller has no buffer in which to store the incoming
message. The MISS bit will be set in CSR0 and an
interrupt will be generated if IENA = 1 (CSR0) and
MISSM = 0 (CSR3). Another poll of the current RDTE
will not occur until the packet has finished.
If the PCnet-ISA II controller sees that the last poll
(either a normal poll or the last-ditch effort described in
69