AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 118

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

6
5
4
3
2
1
0
ISACSR6: LED2 Status
Bit
15
14
118
RCVADDM
RVPOL E
LEDOUT
LEDXOR
XMT E
RCV E
COL E
JAB E
Name
RES
0 is disabled, 1 is enabled.
Reserved locations. Read and
written as zero.
Receive Address Match. This bit
when set allows for LED control
of only receive packets which
match internal address match.
Enable Transmit Status Signal.
Indicates PCnet-ISA II controller
transmit activity.
0 disables the signal, 1 enables
the signal.
Enable Receive Polarity Signal.
Enables LED pin assertion when
receive polarity is correct on the
10BASE-T port. Clearing the bit
indicates this function is to be
ignored.
Enable Receive Status Signal.
Indicates receive activity on the
network.
0 disables the signal, 1 enables
the signal.
Enable Jabber Signal. Indicates
the PCnet-ISA II controller is jab-
bering on the network.
0 disables the signal, 1 enables
the signal.
Enable Collision Signal. Indi-
cates collision activity on the
network.
0 disables the signal, 1 enables
the signal.
ISACSR6 controls the func-
tion(s) that the LED2 pin dis-
plays. Multiple functions can be
simultaneously enabled on this
LED pin. The LED display will
indicate the logical OR of the
enabled functions. ISACSR6
defaults to twisted pair MAU
Receive
with pulse stretcher enabled
(PSE = 1) and is fully program-
mable.
Indicates
stretched) state of the func-
tion(s) generated. Read only.
This bit when set causes LED2
to be an active high signal when
asserted.
cleared, LED2 will be active low
when asserted.
Description
Polarity
the
When
current
this
(RCVPOL)
bit
(non-
Am79C961A
is
Note: This bit when used in conjunction with the
RVPOLE bit (Bit 3) of ISACSR6 can be used to create
a “Polarity Bad” LED.)
13-10
9
8
7
6
5
RVPOLE
RCVADDM
0
1
1
FDLSE
RES
RES
PSE
MP
LEDXOR
X
0
1
Reserved locations. Read and
written as zero.
Magic Packet LED Enable.
When set, the LED output will be
asserted to indicate that a Magic
Packet has been received.
Full Duplex Link Status Enable.
Indicates the Full Duplex Link
Test Status. When this bit is set,
a value of ONE is passed to the
LEDOUT signal when the PC-
net-ISA II is functioning in a link
pass state with Full Duplex ca-
pability. When the PCnet-ISA II
is not functioning in a link pass
state with Full Duplex capability,
a value of ZERO is passed to the
LEDOUT signal.
When the 10BASE-T port is
active, a value of ONE is passed
to the LEDOUT signal whenever
the Link Test Function (described
in the T-MAU section) detects a
Link Pass state and the FDEN
(ISACSR9, bit 0) bit is set. When
the AUI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex oper-
ation on the AUI port is enabled
(both FDEN and AUIFD bits in
ISACSR9 are set to ONE). When
the GPSI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex oper-
ation on the GPSI port is enabled
(FDEN bit in ISACSR9 is set to
ONE).
Pulse Stretcher Enable. Extends
the LED illumination for each
enabled function occurrence.
0 is disabled, 1 is enabled.
Reserved locations. Read and
written as zero.
Receive Address Match. This bit
when set allows for LED control
Result
10BASE-T polarity function
ignored
LED2 pin low with “Good”
10BASE-T polarity (LED on)
LED2 pin high with “Good”
10BASE-T polarity (LED off)