AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 105

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

2
1
0
LOOP
0
1
1
1
LOOP
DRX
DTX
INTL
X
0
1
1
MENDECL
In loopback mode, this bit deter-
mines if the transmitter appends
FCS or if the receiver checks the
FCS.
This bit was called DTCR in the
LANCE (Am7990).
Read/write
when STOP or SPND bits are
set.
Loopback Enable allows PC-
net-ISA II controller to operate in
full duplex mode for test purpos-
es. When LOOP = “1", loopback
is enabled. In combination with
INTL and MENDECL, various
loopback modes are defined as
follows.
Read/write
when STOP or SPND bits are
set. LOOP is cleared by RESET.
Disable Transmit. If this bit is set,
the PCnet-ISA II controller will
not
Descriptor Ring and, therefore,
no transmissions will occur. DTX
= “0" will set TXON bit (CSR0.4)
after STRT (CSR0.1) is assert-
ed. DTX is defined after the ini-
tialization block is read.
Read/write
when STOP or SPND bits are
set.
Disable Receiver. If this bit is
set, the PCnet-ISA II controller
will not access the Receive
Descriptor Ring and, therefore,
all receive frame data are
ignored. DRX = “0" will set
RXON bit (CSR0.5) after STRT
(CSR0.1) is asserted. DRX is
defined after the initialization
block is read.
Read/write
when STOP or SPND bits are
set.
X
X
0
1
access
Non-loopback
External Loopback
Internal Loopback
Include MENDEC
Internal Loopback
Exclude MENDEC
Loopback Mode
accessible
accessible
accessible
accessible
the
Transmit
only
only
only
only
Am79C961A
CSR16: Initialization Block Address Lower
Bit
15-0
CSR17: Initialization Block Address Upper
Bit
15-8
7-0
CSR18-19: Current Receive Buffer Address
Bit
31-24
23-0
CSR20-21: Current Transmit Buffer Address
Bit
31-24
23-0
CRBA
CXBA
Name
Name
Name
Name
IADR
IADR
RES
RES
RES
Lower 16 bits of the address of
the Initialization Block. Bit loca-
tion 0 must be zero. This register
is an alias of CSR1. Whenever
this register is written, CSR1 is
updated with CSR16’s contents.
Read/Write
when the STOP or SPND bits
are set. Unaffected by RESET.
Reserved locations. Written as
zero and read as undefined.
Upper 8 bits of the address of
the Initialization Block. Bit loca-
tions 15-8 must be written with
zeros. This register is an alias of
CSR2. Whenever this register is
written, CSR2 is updated with
CSR17’s contents.
Read/Write
when the STOP or SPND bits
are set. Unaffected by RESET.
Reserved locations. Written as
zero and read as undefined.
Contains the current receive
buffer address to which the PC-
net-ISA II controller will store in-
coming frame data.
Read/write accessible only when
STOP or SPND bits are set.
Reserved locations. Written as
zero and read as undefined.
Contains the current transmit
buffer address from which the
PCnet-ISA II controller is trans-
mitting.
Read/write accessible only when
STOP or SPND bits are set.
Description
Description
Description
Description
accessible
accessible
only
only
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