AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 88

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

ISA Configuration Register Cycles
The ISA configuration register is accessed by placing
the address of the desired register into the RAP and
reading the IDP. The ISACSR bus cycles are identical
to all other PCnet-ISA II controller register bus cycles.
Boot PROM Cycles
The Boot PROM is an 8-bit PROM connected to the
PCnet-ISA II controller Private Data Bus (PRDB), and
can occupy up to 64 Kbytes of address space. In
Shared Memory Mode, an external address compara-
tor is responsible for asserting BPAM to the PCnet-ISA
II controller. BPAM is intended to be a perfect decode
of the boot PROM address space, i.e. LA17-23, SA16.
The LA bus must be latched with BALE in order to pro-
vide stable signal for BPAM. REF inactive must be
used by the external logic to gate boot PROM address
decoding. This same logic must assert MEMCS16 to
the ISA bus if 16-bit Boot PROM bus cycles are
desired.
In the Bus Slave mode, boot PROM cycles can be pro-
grammed to be 8 or 16-bit ISA memory cycles with the
BP_16B bit (PnP 0x42). If the BP_16B bit is set, the
PCnet-ISA II assumes 16-bit ISA memory cycles for
the boot PROM. In this case, the external hardware
responsible for generating BPAM must also generate
MEMCS16. A 16-bit boot PROM bus cycle begins with
the Permanent Master driving the addresses valid and
MEMR active. (AEN is not involved in memory cycles).
External hardware would assert BPAM and MEMCS16.
The PCnet-ISA II controller detects this combination of
signals, drives IOCHRDY LOW, and reads two bytes
out of the boot PROM. The data bytes read from the
PROM are driven by the PCnet-ISA II controller onto
SD0-15 and IOCHRDY is released. This condition is
maintained until MEMR goes inactive, at which time the
access cycle ends.
The PCnet-ISA II controller will perform 8-bit ISA bus
cycle operation for all resource (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
The BPCS signal generated by the PCnet-ISA II con-
troller is three 20 MHz clock cycles wide (350 ns).
Including delays, the Boot PROM has 275 ns to
respond to the BPCS signal from the PCnet-ISA II con-
troller. This signal is intended to be connected to the
CS pin on the boot PROM, with the PROM OE pin tied
to ground.
Static RAM Cycles – Shared Memory Architecture
In the Shared Memory Architecture mode, the SRAM is
an 8-bit device connected to the PCnet-ISA II controller
Private Bus, and can occupy up to 64 Kbytes of
address space. The SRAM is memory mapped into the
ISA memory space at an address range determined by
external decode logic. The external address compara-
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Am79C961A
tor is responsible for asserting SMAM to the PCnet-ISA
II controller. SMAM is intended to be a perfect decode
of the SRAM address space, i.e. LA17-23, SA16 for 64
Kbytes of SRAM. The LA signals must be latched by
BALE in order to provide a stable decode for SMAM.
The PCnet-ISA II controller assumes 16-bit ISA mem-
ory bus cycles for the SRAM, so this same logic must
assert MEMCS16 to the ISA bus if 16-bit bus cycles are
to be supported.
A 16-bit SRAM bus cycle begins with the Permanent
Master driving the addresses valid, REF inactive, and
either MEMR or MEMW active. (AEN is not involved in
memory cycles). External hardware would assert
SMAM and MEMCS16. The PCnet-ISA II controller
detects this combination of signals and initiates the
SRAM access.
In a write cycle, the PCnet-ISA II controller stores the
data into an internal holding register, allowing the ISA
bus cycle to finish normally. The data in the holding reg-
ister will then be written to the SRAM without the need
for ISA bus control. In the event the holding register is
already filled with unwritten SRAM data, the PCnet-ISA
II controller will extend the ISA write cycle by driving
IOCHRDY LOW until the unwritten data is stored in the
SRAM. The current ISA bus cycle will then complete
normally.
In a read cycle, the PCnet-ISA II controller arbitrates for
the Private Bus. If it is unavailable, the PCnet-ISA II
controller drives IOCHRDY LOW. The PCnet-ISA II
controller compares the 16 bits of address on the Sys-
tem Address Bus with that of a data word held in an
internal pre-fetch register.
If the address does not match that of the prefetched
SRAM data, then the PCnet-ISA II controller drives
IOCHRDY LOW and reads two bytes from the SRAM.
The PCnet-ISA II controller then proceeds as though
the addressed data location had been prefetched.
If the internal prefetch buffer contains the correct data,
then the pre-fetch buffer data is driven on the System
Data bus. If IOCHRDY was previously driven LOW due
to either Private Data Bus arbitration or SRAM access,
then it is released HIGH. The PCnet-ISA II controller
remains in this state until MEMR is de-asserted, at
which time the PCnet-ISA II controller performs a new
prefetch of the SRAM. In this way memory read wait
states can be minimized.
The PCnet-ISA II controller performs prefetches of the
SRAM between ISA bus cycles. The SRAM is
prefetched in an incrementing word address fashion.
Prefetched data are invalidated by any other activity on
the Private Bus, including Shared Memory Writes by
either the ISA bus or the network interface, and also
address and boot PROM reads.