AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 60

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

Plug & Play Register Locations Detailed
Description (Refer to the Plug & Play
Register Map above)
IOAM[3:0]
IRQ[3:0]
IRQ Type
IRQ_LVL
DMA[2:0]
60
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IRQ[3:0]
0
1
1
0
0
0
1
1
IOAM[3:0]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ISA IRQ Pin
IRQ3 (Default)
IRQ4
IRQ5
IRQ9
IRQ10
IRQ11
IRQ12
IRQ15
I/O Address Match to bits [8:5] of SA
bus (PnP 0x60–0x61). Controls the
base address of PCnet-ISA II. The
IOAM will be written with a value
from the EEPROM.
IRQ selection on the ISA bus (PnP
0x70). Controls which interrupt will
be asserted. ISA Edge sensitive or
EISA level mode is controlled by
IRQ_TYPE bit in PnP 0x71. Default
is ISA Edge Sensitive. The IRQ sig-
nals will not be driven unless PnP
activate register bit is set.
IRQ Type(PnP 0x71). Indicates the
type of interrupt setting; Level is 1,
Edge is 0.
IRQ Level (PnP 0x71). A read-only regis-
ter bit that indicates the type of setting, ac-
tive high or low. Always complement of
IRQ_TYPE. See ISA CSR2 (EISA_LVL).
DMA Channel Select (PnP 0x74).
Controls the DRQ and DMA selec-
tion of PCnet-ISA II. The DMA[2:0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
220
2C0
360
Base Address (Hex)
240
280
2A0
2E0
300
340
380
3C0
200
260
320
3A0
3E0
Am79C961A
BPAM[3:0]
BP_16B
BPSZ[3:0]
SRAM[4:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
BPAM[3:0]
DMA[2:0]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BPSZ[3:0]
x
1
1
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
1
1
0
0
1
1
0
1
0
Selects the location where the Boot
PROM Address match decode is
started. The BPAM will be written
with a value from the EEPROM.
0x42). Is asserted if Boot PROM
cycles should respond as an 16-bit
device. In Bus Master mode, all boot
PROM cycles will only be 8 bits in
width.
Selects the size of the boot PROM
selected.
[17:13] of SA bus (PnP 0x48-0x49).
Selects the starting location of the
Shared Memory when using the
register will be written with a value
from the EEPROM. {For Bus Master
Mode Only} The DRQ signals will
not be driven unless Plug and Play
activate register bit is set.
Boot PROM Address Match to bits
[16:13] of SA bus (PnP 0x40–0x41).
Boot PROM 16-bit access (PnP
Boot PROM Size (PnP 0x43–0x44).
Static RAM Address Match to bits
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Location (Hex)
x
1
0
0
0
DMA Channel (DRQ/DACK Pair)
Address
CC000
DC000
CA000
CE000
DA000
DE000
C0000
C2000
C4000
C6000
C8000
D0000
D2000
D4000
D6000
D8000
Boot PROM Size
No Boot PROM Selected
8 K
16 K
32 K
64 K
No DMA Channel
Channel 3
Channel 5
Channel 6
Channel 7
Size Supported
(K bytes)
8, 16, 32, 64
8
8, 16
8
8, 16, 32
8
8, 16
8
8, 16, 32, 64
8
8, 16
8
8, 16, 32
8
8, 16
8