AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 82

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access
Port is provided for board-level continuity test and diag-
nostics. All digital input, output, and input/output pins are
tested. Analog pins, including the AUI differential driver
(DO ) and receivers (DI , CI ), and the crystal input
(XTAL1/XTAL2) pins, are tested. The T-MAU drivers
TXD , TXP , and receiver RXD are also tested.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the PC-
net-ISA II controller.
Boundary Scan Circuit
The boundary scan test circuit requires four extra pins
(TCK, TMS, TDI and TDO), defined as the Test Access
Port (TAP). It includes a finite state machine (FSM), an
instruction register, a data register array, and a
power-on reset circuit. Internal pull-up resistors are
provided for the TDI, TCK, and TMS pins. The TCK pin
must not be left unconnected. The boundary scan cir-
cuit remains active during sleep.
TAP FSM
The TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power-up or RESET. An
independent power-on reset circuit is provided to
ensure the FSM is in the TEST_LOGIC_RESET state
at power-up.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST and SAMPLE instructions), three
Power Saving Modes
The PCnet-ISA II controller supports two hardware
power-savings modes. Both are entered by asserting
the SLEEP pin LOW.
In coma mode, the PCnet-ISA II controller will go into
deep sleep with no support to automatically wake itself
up. Sleep mode is enabled when the AWAKE bit in
82
Instruction
SAMPLE
SETBYP
EXTEST
IDCODE
BYPASS
TRIBYP
Name
External Test
ID Code Inspection
Sample Boundary
Force Tristate
Control Boundary to 1/0
Bypass Scan
Description
IEEE 1149.1 Supported Instruction Summary
Am79C961A
Data Reg
a d d i t i o n a l i n s t r u c t i o n s ( I D C O D E , T R I B Y P
and SETBYP) are provided to further ease board-level
testing. All unused instruction codes are reserved. See
the table below for a summary of supported instructions.
Instruction Register and Decoding Logic
After hardware or software RESET, the IDCODE
instruction is always invoked. The decoding logic gives
signals to control the data flow in the DATA registers
according to the current instruction.
Boundary Scan Register (BSR)
Each BSR cell has two stages. A flip-flop and a latch are
used in the SERIAL SHIFT STAGE and the PARALLEL
OUTPUT STAGE, respectively.
There are four possible operational modes in the BSR cell:
Other Data Registers
(1) BYPASS REG (1 BIT)
(2) DEV ID REG (32 bits)
Selected
ISACSR2 is reset. This mode is the default powerdown
mode.
In Snooze mode, enabled by setting the AWAKE bit in
ISACSR2 and driving the SLEEP pin LOW, the T-MAU
receive circuitry will remain enabled even while the
SLEEP pin is driven LOW. The LED0 output will also
continue to function, indicating a good 10BASE-T link if
ID REG
Bits 31–28:
Bits 27–12:
Bits 11–1:
Bit 0:
Bypass
Bypass
Bypass
BSR
BSR
1
2
3
4
Capture
Shift
Update
System Function
Version
Part number (2261h)
Manufacturer ID. The 11 bit
manufacturer ID code for AMD is
00000000001 according to JEDEC
Publication 106-A.
Always a logic 1
Normal
Normal
Normal
Normal
Mode
Test
Test
Instruction
Code
0000
0001
0010
0011
0100
1111