AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 122

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

Receive Descriptors
The Receive Descriptor Ring Entries (RDREs) are
composed of four receive message fields (RMD0-3).
Together they contain the following information:
RMD0
Holds LADRF [15:0]. This is combined with HADR [7:0]
in RMD1 to form the 24-bit address of the buffer
pointed to by this descriptor table entry. There are no
restrictions on buffer byte alignment or length.
RMD1
Bit
15
14
13
12
122
The address of the actual message data buffer in
user (host) memory
The length of that message buffer
Status information indicating the condition of the
buffer. The eight most significant bits of RMD1
(RMD1[15:0]) are collectively termed the STATUS
of the receive descriptor.
FRAM
OFLO
Name
OWN
ERR
This bit indicates that the descrip-
tor entry is owned by the host
(OWN=0) or by the PCnet-ISA II
controller (OWN=1). The PCnet-
ISA II controller clears the OWN
bit after filling the buffer pointed
to by the descriptor entry. The
host sets the OWN bit after emp-
tying the buffer. Once the PC-
net-ISA II controller or host has
relinquished ownership of a buff-
er, it must not change any field in
the descriptor entry.
ERR is the OR of FRAM, OFLO,
CRC, or BUFF. ERR is written
by the PCnet-ISA II controller.
FRAMING ERROR indicates
that the incoming frame con-
tained a non-integer multiple of
eight bits and there was an FCS
error. If there was no FCS error
on the incoming frame, then
FRAM will not be set even if
there was a non integer multiple
of eight bits in the frame. FRAM
is not valid in internal loopback
mode. FRAM is valid only when
ENP is set and OFLO is not.
FRAM is written by the PC-
net-ISA II controller.
OVERFLOW error indicates that
the receiver has lost all or part of
the incoming frame, due to an
inability to store the frame in a
memory buffer before the inter-
nal FIFO overflowed. OFLO is
valid only when ENP is not set.
Description
Am79C961A
11
10
9
8
7-0
RMD2
Bit
15-12 ONES
HADR
BUFF
Name
CRC
ENP
STP
OFLO is written by the PC-
net-ISA II controller.
CRC indicates that the receiver
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is written by
the PCnet-ISA II controller.
BUFFER ERROR is set any time
the PCnet-ISA II controller does
not own the next buffer while
data chaining a received frame.
This can occur in either of two
ways:
1) The OWN bit of the next
2) FIFO overflow occurred
If a Buffer Error occurs, an Over-
flow Error may also occur inter-
nally in the FIFO, but will not be
reported in the descriptor status
entry unless both BUFF and
OFLO errors occur at the same
time. BUFF is written by the PC-
net-ISA II controller.
START OF PACKET indicates
that this is the first buffer used by
the PCnet-ISA II controller for
this frame. It is used for data
chaining buffers. STP is written
by the PCnet-ISA II controller in
normal operation. In SRPINT
Mode (CSR3.5 set to 1) this bit is
written by the driver.
END OF PACKET indicates that
this is the last buffer used by the
PCnet-ISA II controller for this
frame. It is used for data chain-
ing buffers. If both STP and ENP
are set, the frame fits into one
buffer and there is no data chain-
ing. ENP is written by the PC-
net-ISA II controller.
The HIGH ORDER 8 address
bits of the buffer pointed to by
this descriptor. This field is writ-
ten by the host and is not
changed by the PCnet-ISA II
controller.
MUST BE ONES. This field is
written
buffer is zero
before the PCnet-ISA II
controller polled the next
descriptor
by
Description
the
host
and