AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 98

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

2
1
0
CSR1: IADR[15:0]
Bit
15-0 IADR [15:0]
CSR2: IADR[23:16]
Bit
15-8
98
STOP
STRT
Name
Name
RES
INIT
TDMD is cleared by RESET or
by setting the STOP bit.
STOP assertion disables the
chip from all external activity.
The chip remains inactive until
either STRT or INIT are set. If
STOP, STRT and INIT are all set
together, STOP will override
STRT and INIT.
STOP is set by writing a “1" or by
RESET. Writing a “0" has no ef-
fect. STOP is cleared by setting
either STRT or INIT.
STRT assertion enables PCnet-
ISA II controller to send and
receive frames, and perform
buffer management operations.
Setting STRT clears the STOP
bit. If STRT and INIT are set to-
gether, PCnet-ISA II controller
initialization will be performed
first.
STRT is set by writing a “1". Writ-
ing a “0" has no effect. STRT is
cleared by RESET or by setting
the STOP bit.
INIT assertion enables PC-
net-ISA II controller to begin the
initialization procedure which
reads in the initialization block
from
clears the STOP bit. If STRT and
INIT are set together, PCnet-ISA
II controller initialization will be
performed first. INIT is not
cleared when the initialization
sequence has completed.
INIT is set by writing a “1". Writ-
ing a “0" has no effect. INIT is
cleared by RESET or by setting
the STOP bit.
Lower address of the Initializa-
tion address register. Bit location
0 must be zero. Whenever this
register is written, CSR16 is
updated with CSR1’s contents.
Read/Write
when the STOP or SPND bits
are set. Unaffected by RESET.
Reserved locations. Read and
written as zero.
memory.
Description
Description
accessible
Setting
INIT
only
Am79C961A
7-0 IADR [23:16]
CSR3: Interrupt Masks and Deferral Control
Bit
15
14
13
12
11
10
9
8
7
6
DXSUFLO
MERRM
BABLM
IDONM
MISSM
RINTM
TINTM
Name
RES
RES
RES
Upper 8 bits of the address of
the Initialization Block. Bit loca-
tions 15-8 must be written with
zeros. Whenever this register is
written, CSR17 is updated with
CSR2’s contents.
Read/Write
when the STOP or SPND bits
are set. Unaffected by RESET.
Reserved location. Written as
zero and read as undefined.
Babble Mask. If BABLM is set,
the BABL bit in CSR0 will be
masked and will not set INTR
flag in CSR0.
BABLM is cleared by RESET
and is not affected by STOP.
Reserved location. Written as
zero and read as undefined.
Missed Frame Mask. If MISSM
is set, the MISS bit in CSR0 will
be masked and will not set INTR
flag in CSR0.
MISSM is cleared by RESET
and is not affected by STOP.
Memory Error Mask. If MERRM
is set, the MERR bit in CSR0 will
be masked and will not set INTR
flag in CSR0.
MERRM is cleared by RESET
and is not affected by STOP.
Receive
RINTM is set, the RINT bit in
CSR0 will be masked and will
not set INTR flag in CSR0.
RINTM is cleared by RESET
and is not affected by STOP.
Transmit
TINTM is set, the TINT bit in
CSR0 will be masked and will
not set INTR flag in CSR0.
TINTM is cleared by RESET and
is not affected by STOP.
Initialization
IDONM is set, the IDON bit in
CSR0 will be masked and will
not set INTR flag in CSR0.
IDONM is cleared by RESET
and is not affected by STOP.
Reserved locations. Written as
zero and read as undefined.
Disable
Underflow error.
Transmit
Description
Interrupt
Interrupt
accessible
Done
Mask.
Stop
Mask.
Mask.
only
on
If
If
If