AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 47

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

Bus Slave Mode
System Interface
The Bus Slave mode is the other fundamental operat-
ing mode available on the PCnet-ISA II controller.
Within the Bus Slave mode, the PCnet-ISA II can be
programmed for a Shared Memory or Programmed I/O
architecture. In the Bus Slave mode the PCnet-ISA II
controller uses the same descriptor and buffer architec-
ture as in the Bus Master mode, but these data struc-
tures are stored in a static RAM controlled by the
PCnet-ISA II controller. When operating with the
Shared Memory architecture, the local SRAM is visible
as a memory resource on the PC which can be
accessed through memory cycles on the ISA bus inter-
face. When operating with the Programmed I/O archi-
tecture, the local SRAM is accessible through I/O
cycles on the ISA bus. Specifically, the SRAM is acces-
sible using the RAP and IDP I/O ports to access the
ISACSR0 and ISACSR1 registers, which serve as the
SRAM Data port and SRAM Address Pointer port,
respectively.
In the Bus Slave mode, the PCnet-ISA II registers and
optional Ethernet physical address PROM look the
same and are accessed in the same way as in the Bus
Master mode.
The Boot PROM is selected by an external device
which drives the Boot PROM Address Match (BPAM)
input to the PCnet-ISA II controller. The PCnet-ISA II
controller can perform two 8-bit accesses from the 8-bit
Boot PROM and present 16-bits of data to accommo-
date 16 bit read accesses on the ISA bus.
When using the Shared Memory architecture mode,
access to the local SRAM works the same way as
access to the Boot PROM, with an external device gen-
erating the Shared Memory Address Match (SMAM)
signal and the PCnet-ISA II controller performing the
SRAM read or write and the 8/16 bit data conversion.
External logic must also drive MEMCS16 appropriately
for the 128Kbyte segment decoded from the LA[23:17]
signals.
Am79C961A
The Programmed I/O architecture mode uses the RAP
and IDP ports to allow access to the local SRAM
hence, external address decoding is not necessary and
the SMAM pin is not used in Programmed I/O architec-
ture mode (SMAM should be tied HIGH in the Pro-
grammed I/O architecture mode). Similar to the Shared
Memory architecture mode, in the Programmed I/O ar-
chitecture mode, 8/16 bit conversion occurs when 16
bit reads and writes are performed on the SRAM Data
Port (ISACSR1).
Converting the local SRAM accesses from 8-bit cycles
to 16-bit cycles allows use of the much faster 16-bit
cycle timing while cutting the number of bus cycles in
half. This raises performance to more than 400% of
what could be achieved with 8-bit cycles. When the
Shared Memory architecture mode is used, converting
boot PROM accesses to 16-bit cycles allows the two
memory resources to be in the same 128 Kbyte block
of memory without a clash between two devices with
different data widths.
The PCnet-ISA II prefetches data from the SRAM to
allow fast, minimum wait-state read accesses of con-
secutive SRAM addresses. In both the Shared Memory
architecture and the Programmed I/O architecture,
prefetch data is read from a speculated address that
assumes that successive reads in time will be from
adjacent ascending addresses in the SRAM. At the
beginning of each SRAM read cycle, the PCnet-ISA II
determines whether the prefetched data can be
assumed to be valid. If the prefetched data can be
assumed to be valid, it is driven onto the ISA bus
without inserting any wait states. If the prefetched data
cannot be assumed to be valid, the PCnet-ISA II will in-
sert wait states into the ISA bus read cycle until the
correct word is read from the SRAM.
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