AD9910/PCBZ Analog Devices Inc, AD9910/PCBZ Datasheet - Page 6

Direct Digital Synthesis Evaluation Board

AD9910/PCBZ

Manufacturer Part Number
AD9910/PCBZ
Description
Direct Digital Synthesis Evaluation Board
Manufacturer
Analog Devices Inc
Series
AgileRF™r
Datasheets

Specifications of AD9910/PCBZ

Silicon Manufacturer
Analog Devices
Application Sub Type
Direct Digital Synthesizer
Kit Application Type
Clock & Timing
Silicon Core Number
AD9910
Kit Contents
Board
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Main Purpose
Timing, Direct Digital Synthesis (DDS)
Embedded
No
Utilized Ic / Part
AD9910
Primary Attributes
14-Bit DAC, 32-Bit Tuning Word Width
Secondary Attributes
1GHz, Graphical User Interface
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
Q3335404
AD9910
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) = 3.3 V ± 5%, DVDD_I/O (3.3 V) = 3.3 V ± 5%, T = 25°C, R
I
Table 1.
Parameter
REFCLK INPUT CHARACTERISTICS
REFCLK MULTIPLIER VCO CHARACTERISTICS
REFCLK_OUT CHARACTERISTICS
DAC OUTPUT CHARACTERISTICS
OUT
Frequency Range
Input Capacitance
Input Impedance
Duty Cycle
REFCLK Input Level
Maximum Capacitive Load
Maximum Frequency
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Residual Phase Noise
Voltage Compliance Range
Wideband SFDR
Narrow-Band SFDR
External Crystal
VCO Gain (K
= 20 mA, external reference clock frequency = 1000 MHz with reference clock (REFCLK) multiplier disabled, unless otherwise noted.
REFCLK Multiplier
Maximum REFCLK Input Divider Frequency
Minimum REFCLK Input Divider Frequency
REFCLK Multiplier
50.1 MHz Analog Output
101.3 MHz Analog Output
V
) @ Center Frequency
Conditions/Comments
Disabled
Enabled
Full temperature range
Full temperature range
Differential
Single-ended
REFCLK multiplier disabled
REFCLK multiplier enabled
Single-ended
Differential
VCO range Setting 0
VCO range Setting 1
VCO range Setting 2
VCO range Setting 3
VCO range Setting 4
VCO range Setting 5
@ 1 kHz offset, 20 MHz A
Disabled
Enabled @ 20×
Enabled @ 100×
See the Typical Performance
Characteristics section
±500 kHz
±125 kHz
±12.5 kHz
±500 kHz
±125 kHz
±12.5 kHz
Rev. C | Page 6 of 64
1
OUT
Min
100
8.6
−10
−0.5
60
3.2
1500
45
40
50
Typ
1900
25
25
3
2.8
1.4
429
500
555
750
789
850
20
25
20
0.8
1.5
5
−152
−140
−140
–87
–87
–96
–87
–87
–95
Max
1000
60
35
55
60
1000
2000
31.6
+10
2.3
+0.5
MHz
MHz/V
MHz/V
MHz/V
MHz/V
Unit
MHz
MHz
MHz
MHz
pF
%
%
mV p-p
mV p-p
MHz/V
MHz/V
pF
MHz
mA
% FS
μA
LSB
LSB
pF
dBc/Hz
dBc/Hz
dBc/Hz
V
dBc
dBc
dBc
dBc
dBc
dBc
SET
= 10 kΩ,

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