AD9910/PCBZ Analog Devices Inc, AD9910/PCBZ Datasheet - Page 50

• Manufacturer Part Number: AD9910/PCBZ
• Description: Direct Digital Synthesis Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9910/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Direct Digital Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9910
• Kit Contents: Board
• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9910
• Primary Attributes: 14-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 1GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: Q3335404

AD9910
REGISTER MAP AND BIT DESCRIPTIONS
Table 17. Register Map
Register
Name
(Serial
Address)
CFR1—
Control
Function
Register 1
(0x00)
CFR2—
Control
Function
Register 2
(0x01)
CFR3—
Control
Function
Register 3
(0x02)
Auxiliary
DAC
Control
(0x03)
I/O Update
Rate (0x04)
FTW—
Frequency
Tuning
Word
(0x07)
Bit Range
(Internal
Address)
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
Bit 7
(MSB)
RAM
enable
Manual
OSK
external
control
Load LRR
@ I/O
update
Digital
power-
down
Internal
I/O
update
active
Matched
latency
enable
REFCLK
input
divider
bypass
I/O update rate control
Open
Open
Bit 6
Inverse
sinc filter
enable
Autoclear
digital
ramp
accumu-
lator
DAC
power-
down
SYNC_CLK
enable
Data
assembler
hold last
value
REFCLK
input
divider
ResetB
RAM playback
destination
Bit 5
Open
Autoclear
phase
accumu-
lator
REFCLK
input
power-
down
Sync
timing
validation
disable
Digital ramp destination
DRV0[1:0]
Rev. C | Page 50 of 64
Open
Frequency tuning word[31:24]
Frequency tuning word[23:16]
Frequency tuning word[15:8]
Frequency tuning word[7:0]
Bit 4
Clear
digital
ramp
accumu-
lator
Aux DAC
power-
down
Parallel
data port
enable
I
I/O update rate[31:24]
I/O update rate[23:16]
Open
CP
N[6:0]
Open
I/O update rate[15:8]
I/O update rate[7:0]
[2:0]
FSC[7:0]
Open
Open
Open
Bit 3
Clear
phase
accumu-
lator
External
power-
down
control
Digital
ramp
enable
PDCLK
enable
Open
Internal profile control
Bit 2
Load ARR
@ I/O
update
Open
Digital
ramp
no-dwell
high
PDCLK
invert
PFD reset
Open
FM gain
VCO SEL[2:0]
Bit 1
OSK
enable
SDIO input
only
Digital
ramp
no-dwell
low
TxEnable
invert
Open
Open
Bit 0 (LSB)
Select DDS
sine output
Select auto
OSK
LSB first
Enable
amplitude
scale from
single tone
profiles
Read
effective
FTW
Open
PLL enable
Open
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0x40
0x08
0x20
0x1F
0x3F
0x40
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
1