AD9910/PCBZ Analog Devices Inc, AD9910/PCBZ Datasheet - Page 41

• Manufacturer Part Number: AD9910/PCBZ
• Description: Direct Digital Synthesis Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9910/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Direct Digital Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9910
• Kit Contents: Board
• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9910
• Primary Attributes: 14-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 1GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: Q3335404

RAM Continuous Recirculate Mode
The continuous recirculate mode mimics the ramp-up mode,
except that when the state machine reaches the waveform end
address, the next timeout of the internal timer causes the state
machine to jump to the waveform start address. The waveform
repeats until an I/O update or profile change.
The no-dwell high bit is ignored in this mode.
A profile pin state change aborts the current waveform, and the
newly selected RAM profile is used to initiate a new waveform.
The RAM_SWP_OVR pin pulses high for two DDS clock cycles
when the state machine reaches the waveform end address.
Continuous recirculate mode is graphically represented in
Figure 48. The circled numbers indicate specific events as
follows:
RAM_SWP_OVER
RAM ADRESS
I/O_UPDATE
WAVEFORM END ADDRESS
1
WAVEFORM START ADDRESS
Figure 48. Continuous Recirculate Timing Diagram
M DDS CLOCK CYCLES
1
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Δ
t
2
3
Event 1—An I/O update or profile change occurs. This event
initializes the state machine to the waveform start address and
sets the RAM_SWP_OVR pin to Logic 0.
Event 2—The state machine reaches the waveform end address
value for the selected profile. The RAM_SWP_OVR pin toggles
to Logic 1 for two DDS clock cycles.
Event 3—The state machine switches to the waveform start
address and continues to increment the address counter.
Event 4—The state machine again reaches the waveform end
address value for the selected profile, and the RAM_SWP_OVR
pin toggles to Logic 1 for two DDS clock cycles.
Event 5—The state machine switches to the waveform start
address and continues to increment the address counter.
Event 4 and Event 5—These events repeat until an I/O update is
issued or a change in profile is made.
4
5
AD9910