AD9910/PCBZ Analog Devices Inc, AD9910/PCBZ Datasheet - Page 49

• Manufacturer Part Number: AD9910/PCBZ
• Description: Direct Digital Synthesis Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9910/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Direct Digital Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9910
• Kit Contents: Board
• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9910
• Primary Attributes: 14-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 1GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: Q3335404

I/O_RESET—Input/Output Reset
I/O_RESET synchronizes the I/O port state machines without
affecting the contents of the addressable registers. An active
high input on the I/O_RESET pin causes the current communica-
tion cycle to abort. After I/O_RESET returns low (Logic 0),
another communication cycle can begin, starting with the
instruction byte write.
I/O_UPDATE—Input/Output Update
The I/O_UPDATE initiates the transfer of written data from
the I/O port buffer to active registers. I/O_UPDATE is active
on the rising edge, and its pulse width must be greater than one
SYNC_CLK period. It is either an input or output pin depending
on the programming of the internal I/O update active bit.
SCLK
SDIO
SCLK
SCLK
SCLK
SDO
SDIO
SDIO
SDIO
CS
CS
CS
CS
I
I
7
7
I
7
I
7
I
I
6
6
I
6
I
6
I
INSTRUCTION CYCLE
INSTRUCTION CYCLE
5
I
INSTRUCTION CYCLE
INSTRUCTION CYCLE
5
I
5
I
5
Figure 58. 2-Wire Serial Port Read Timing, Clock Stall High
Figure 56. 3-Wire Serial Port Read Timing, Clock Stall Low
I
I
4
4
I
4
Figure 57. Serial Port Write Timing, Clock Stall High
Figure 55. Serial Port Write Timing, Clock Stall Low
I
4
I
I
3
3
I
3
I
3
I
I
2
2
I
2
I
2
Rev. C | Page 49 of 64
I
I
1
1
I
1
I
1
I
I
0
0
I
0
I
0
D
D
D
O7
7
SERIAL I/O TIMING DIAGRAMS
Figure 55 through Figure 58 provide basic examples of the timing
relationships between the various control signals of the serial
I/O port. Most of the bits in the register map are not transferred
to their internal destinations until assertion of an I/O update,
which is not included in the timing diagrams that follow.
MSB/LSB TRANSFERS
The AD9910 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 0 in Control Function Register 1
(0x00). The default format is MSB first. If LSB first is active, all
data, including the instruction byte, must follow LSB-first conven-
tion. Note that the highest number found in the bit range column
for each register is the MSB, and the lowest number is the LSB
for that register (see the Register Map and Bit Descriptions
section and Table 17).
7
D
O7
D
D
6
O6
D
D
DATA TRANSFER CYCLE
6
O6
DATA TRANSFER CYCLE
D
D
DATA TRANSFER CYCLE
5
DATA TRANSFER CYCLE
O5
D
D
5
O5
D
D
DON'T CARE
4
O4
D
D
4
O4
D
D
3
O3
D
D
3
O3
D
D
2
O2
D
D
2
O2
D
D
1
O1
D
D
1
O1
D
0
D
D
O0
D
O0
0
AD9910