AD9910/PCBZ Analog Devices Inc, AD9910/PCBZ Datasheet - Page 40

Direct Digital Synthesis Evaluation Board

AD9910/PCBZ

Manufacturer Part Number
AD9910/PCBZ
Description
Direct Digital Synthesis Evaluation Board
Manufacturer
Analog Devices Inc
Series
AgileRF™r
Datasheets

Specifications of AD9910/PCBZ

Silicon Manufacturer
Analog Devices
Application Sub Type
Direct Digital Synthesizer
Kit Application Type
Clock & Timing
Silicon Core Number
AD9910
Kit Contents
Board
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Main Purpose
Timing, Direct Digital Synthesis (DDS)
Embedded
No
Utilized Ic / Part
AD9910
Primary Attributes
14-Bit DAC, 32-Bit Tuning Word Width
Secondary Attributes
1GHz, Graphical User Interface
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
Q3335404
AD9910
A change in state of the PROFILE pins aborts the current wave-
form, and the newly selected RAM profile is used to initiate a
new waveform.
The RAM_SWP_OVR pin switches to Logic 1 when the state
machine reaches the waveform end address, then returns to
Logic 0 at the waveform start address, toggling each time one
of these addresses is reached.
A graphic representation of the continuous bidirectional ramp
mode is shown in Figure 47. The circled numbers indicate specific
events as follows:
RAM_SWP_OVER
RAM ADRESS
I/O_UPDATE
WAVEFORM END ADDRESS
1
WAVEFORM START ADDRESS
Figure 47. Continuous Bidirectional Ramp Timing Diagram
M DDS CLOCK CYCLES
1
Rev. C | Page 40 of 64
Δ
t
2
Event 1—An I/O update or profile change has activated the RAM
continuous bidirectional ramp mode. The state machine initializes
to the waveform start address. The RAM_SWP_OVR pin resets to
Logic 0. The state machine begins incrementing through the
specified address range.
Event 2—The state machine reaches the waveform end address.
The RAM_SWP_OVR pin toggles to Logic 1.
Event 3—The state machine reaches the waveform start address.
The RAM_SWP_OVR pin toggles to Logic 0.
The continuous bidirectional ramp continues indefinitely until
the mode is changed.
Δ
t
3

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