EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 764

• Manufacturer Part Number: EP9315-IBZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-IBZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 65
• Package / Case: 352-PBGA
• Clock Frequency: 200MHz
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1263

26
26-2
Keypad Interface
EP93xx User’s Guide
26.2 Theory of Operation
The circuitry scans an array of up to 64 keys. The keys are normally open, single pole
contacts arranged in an array of 8 rows by 8 columns. The array may be partially filled. The
key array rows are designated as ROW0 through ROW7, and the columns are designated as
COL0 through COL7.
Any 1 or 2 keys in the array that are pressed are de-bounced and decoded. If more than 2
keys are pressed, only the keys or apparent keys in the array with the lowest address will be
decoded.
Keys or apparent keys with address values greater than that of the lowest two will be ignored.
An apparent key is a condition that may occur when more than 2 keys are pressed. Apparent
keys are caused by alternate current paths in the key array.
A key address is the binary row number concatenated with the binary column address. Key
addresses range from 0x00 to 0x3F. A diagram of the key array is shown in
The circuitry scans the key array by driving each ROW line low, one line at a time. At the end
of each ROW time period, column data is read. The key array column lines are registered and
decoded by a multiplexer. The column address selects the column multiplexer input. Each of
the column lines is passively pulled up by the chip.
When a key is pressed, the column line for the key will be driven low when the row which
contains the key is driven low. On the next key array scan, the output of the multiplexer in the
chip will be asserted active when the row and column is the same as the key address. When
the multiplexer output is active then the key is detected and the address is stored, if it is one
of the first two from the start of a key array scan.
When more than 2 keys are pressed, it is possible to detect apparent keys. Apparent keys
look like actual pressed keys to the device but are not. An example of an apparent key is
described in
“Apparent Key
Detection”.
Copyright 2007 Cirrus Logic
Figure
26-2.
DS785UM1