EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 375

32-Bit Microcontroller IC

EP9315-IBZ

Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-IBZ

Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1263

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
Part Number:
EP9315-IBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
RXDCurAdd
DS785UM1
31
15
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Receive Descriptor Queue Current Length register. The Receive Descriptor
Queue Current Length defines the number of bytes between the Receive
Descriptor Current Address and the end of the receive descriptor queue. This
value is used internally to wrap the pointer back to the start of the queue. The
register should not normally be written.
RSVD:
RDCL:
0x8001_0098 - Read/Write
0x0000_0000
Unchanged
Receive Descriptor Current Address register. The Receive Current Descriptor
Address contains the pointer to the next entry to be read from the receive
descriptor queue. This should be set at initialization time to the required
starting point in the descriptor queue. During operation the MAC will update
this address following successful descriptor reads. Intermediate values in this
register will not necessarily align to descriptor boundaries, nor directly effect
the current descriptor in use because several descriptors may be buffered
inside the MAC.
RDCA:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Receive Descriptor Current Length.
Receive Descriptor Current Address.
24
8
RDCA
RDCA
23
7
22
6
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
9-73
0
9

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