EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 760

32-Bit Microcontroller IC

EP9315-IBZ

Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-IBZ

Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1263

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
Part Number:
EP9315-IBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
25
TSSetup2
25-22
Analog Touch Screen Interface
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
RSVD
29
13
28
12
0x8090_0024
0x0000_0000
Touch screen Setup Register #2.
RSVD:
RINTEN:
S28EN:
NSIGND:
DISDEV:
DTMEN:
DINTEN:
RINTEN
27
11
S28EN
26
10
Copyright 2007 Cirrus Logic
NSIGND
25
9
Reserved. Unknown during read.
Synchronous Data Ready Interrupt Enable. Setting this bit
results in an interrupt whenever the Synchronous Data
Ready (SDR) bit in the TSXYResult register is set. The
SDR bit will never be set unless the EN bit of the TSSetup
register is clear.
Switch 28 Enable. The touch detect NAND gate can be
triggered separately by bit 28 of the switch registers or in
conjunction with bit 22 which also controls the X+ pullup.
0 = NAND gate controlled by bit 22.
1 = NAND gate controlled by bit 28.
Unsigned ADC output type. The touch input information
can be processed as signed or unsigned integers. The
default bit value is “0” for signed.
Disable Deviation check for both X and Y ADC sampling.
Setting this bit high causes the deviation test to always
pass and forces a sample set.
Deviation Timer Enable. Setting this bit high enables the
timeout for the deviation check. If the deviation check fails
255 times for either the X or Y axis the algorithm will skip
this check and force a sample set anyway.
Deviation Error Interrupt Enable. Setting this bit high
causes an interrupt when the sample deviation check fails
255 times for either the X or Y axis. The DTMEN bit must
be high for this bit to be effective.
DISDEV
24
8
RSVD
DTMEN
23
7
DINTEN
22
6
DEVINT
21
5
PINTEN
20
4
PENSTS
19
3
PINT
18
2
NICOR
17
1
DS785UM1
TINT
16
0

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