EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 691

• Manufacturer Part Number: EP9315-IBZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-IBZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 65
• Package / Case: 352-PBGA
• Clock Frequency: 200MHz
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1263

DS785UM1
22.2.1 Channel Interrupts
22.2.1.1 RIS
22.2.1.2 TIS
22.2 Interrupts
transmitted at 48 kHz, the external codec does not have Data Request Disable bits for these
slots. Data for transmission on slots 1, 2, and 12 can be obtained from either the channels or
the registers SLOT1RXTX, AC97S2Data and AC97S12Data. However, consistent usage of
one of these two methods should be maintained.
If the slot enable bits are set when receiving the data for slots 1, 2, and 12, the data is stored
in the channel and not the SLOT1/2/12RX registers. If the slot enable bits are not set, then
the data will always go to the registers.
The user should only use the channels to transmit slot 1 and 2 data when they are setting the
external codec up for operation. Once the set up of the external codec is complete, the data
for slot 1 and 2 should come via the SLOT1/2TX registers. This action frees up the channel.
The AC’97 Controller generates individual maskable active HIGH interrupts. Each interrupt
may be enabled or disabled using the appropriate enable bit. Setting the bit HIGH enables
the corresponding interrupt. This allows for a system interrupt controller to provide the mask
registers for each interrupt.
The status of the individual interrupt sources can be read from appropriate register. The
interrupts are ORed to create one interrupt (AC97INTR) for the AC’97 controller block
The individual interrupts that are generated by each transmit/receive channel are described
below. The status of the interrupts can be read from the AC97RISRx or AC97ISRx registers,
and is masked in the AC97IEx register.
If the receive FIFO is enabled and the mask bit RIE is set, the FIFO receive interrupt is
asserted when the AC’97 Controller receive FIFO is greater than or equal to half full. The
receive interrupt is cleared when the FIFO becomes less than half full.
If the receive FIFO is disabled, it has a depth of one location. Any data received will fill that
one location, causing the receive interrupt to be asserted high. The receive interrupt is
cleared by performing a single read of the receive FIFO.
If the transmit FIFO is enabled and the mask bit TIE is set, the FIFO transmit interrupt is
asserted when the AC’97 Controller transmit FIFO is at least half-empty. The FIFO transmit
interrupt is cleared by filling the transmit FIFO more than half full.
If the transmit FIFO is disabled (has a depth of one location) and there is no data present in
the transmitters single location, the transmit interrupt is asserted high. The transmit interrupt
is cleared by performing a single write to the transmit FIFO.
Copyright 2007 Cirrus Logic
EP93xx User’s Guide
AC’97 Controller
22-3
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