EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 632

• Manufacturer Part Number: EP9315-IBZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-IBZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 65
• Package / Case: 352-PBGA
• Clock Frequency: 200MHz
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1263

17
FIMR
17-36
IrDA
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
RFS:
TAB:
TFC:
TFS:
0x808B_0184 - Read/Write
0x0000_0000
FIR Interrupt Mask Register.
RSVD:
RFL:
RIL:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Receive buffer Service Request (read only).
0 - Receive buffer is empty or the receiver is discarding
data or the receiver is disabled.
1 - Receive buffer is not empty and the receiver is
enabled, DMA service request signaled.
The bit is automatically cleared when the receive buffer is
emptied.
Transmit Frame Aborted. Set to “1” when a transmitted
frame is terminated with an abort. This will only occur if the
TUS bit is set in the IrCtrl register. The bit is cleared by
writing a “1” to this bit.
Transmitted Frame Complete. Set to “1” whenever a
transmitted frame completes (whether it is terminated with
a CRC followed by a stop flag or terminated with an abort).
This bit is cleared by writing a “1” to this bit.
Transmit buffer Service Request (read only).
0 - Transmit buffer is full or transmitter disabled.
1 - Transmit buffer is not full and the transmitter is
enabled, DMA service is signaled.
The bit is automatically cleared after the buffer is filled.
Reserved. Unknown During Read.
RFL mask bit. When high, the FIR RFL status can
generate an interrupt.
RIL mask bit. When high, the FIR RIL status can generate
an interrupt.
24
8
RSVD
23
7
RFL
22
6
RIL
21
5
RFC
20
4
RFS
19
3
TAB
18
2
TFC
17
1
DS785UM1
TFS
16
0