EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 422

• Manufacturer Part Number: EP9315-IBZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-IBZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 65
• Package / Case: 352-PBGA
• Clock Frequency: 200MHz
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1263

10
REMAIN
10-28
DMA Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Channel Base Address + 0x0014 - Read Only
The Channel Bytes Remaining Register contains the number of bytes
remaining in the current DMA transfer. Only the lower 16 bits are valid
RSVD:
REMAIN:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Loaded from the Channel MAXCNT register when the
DMA Channel State Machine enters the ON State.
Although there are 2 Data transfer states, ON and NEXT,
this register need only be assigned in the ON state,
because in this state the next buffer to be used is
determined (there is only one) and this MAXCNT value is
assigned to REMAIN. The DMA State Machine counts
down by one byte every time a byte is transferred between
the DMA Controller and the Peripheral. When this register
reaches zero, the current buffer transfer is complete and
the TxTC/RxTC are generated and used to indicate this to
the peripheral. DMA transfers may also be stopped with
the TxEnd/RxEnd signals from the peripheral, where the
REMAIN register is non-zero at the end of transfer,
allowing software to determine the last valid data in a
buffer.
24
8
REMAIN
RSVD
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0