EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 720

32-Bit Microcontroller IC

EP9315-IBZ

Manufacturer Part Number
EP9315-IBZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-IBZ

Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
65
Package / Case
352-PBGA
Clock Frequency
200MHz
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1263

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
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EP9315-IBZ
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EP9315-IBZ
Manufacturer:
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23
23-8
Synchronous Serial Port
EP93xx User’s Guide
23.5.9 Motorola SPI Format with SPO=1, SPH=0
SFRMOUT /
SCLKOUT /
SFRMIN
Single and continuous transmission signal sequences for Motorola SPI format with SPO=1,
SPH=0 are shown in
In this configuration, during idle periods
SCLKIN
SSPRXD
SSPTXD
Note: In
SSPOE
• the SCLKOUT signal is forced HIGH
• SFRMOUT is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
• when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling
• when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling
SSPOE (=0)
SFRMOUT /
SCLKOUT /
the SCLKOUT pad (active LOW enable)
the SCLKOUT pad (active LOW enable).
SSPTXD /
SSPRXD
SCLKIN
SFRMIN
Figure 23-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
Figure
Figure 23-7. Motorola SPI Frame Format (Continuous Transfer)
23-6, Q is an undefined signal.
LS B
MS B
MS B
Figure 23-6
Copyright 2007 Cirrus Logic
MS B
with SPO=1 and SPH=0
and
Figure
4 t o 16 bi t s
4 t o 16 bi t s
23-7.
LSB
MS B
LS B
LS B
DS785UM1
Q

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