MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 84

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FLASH-2 Memory
5.8 FLASH Block Protection
Technical Data
NOTE:
NOTE:
This program/margin read sequence is repeated throughout the memory
until all data is programmed. The smart programming algorithm shown
in
array. This algorithm ensures the minimum possible program time and
avoids the deleterious program disturb effect. See
Operation.
To ensure the timing requirements of the high-voltage erase and
program mode of the FLASH memory, interrupts must be masked
(interrupt mask bit of CCR = 1) when the HVEN bit is set.
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by reserving a location in the
memory for block protect information and requiring that this location be
read before setting the HVEN bit. When the block protect register is read,
its contents are latched by the FLASH control logic. If the address range
for an erase or program operation includes a protected block, the PGM
or ERASE bit is cleared which prevents the HVEN bit in the FLASH
control register from being set so that no high voltage is allowed in the
array.
When the block protect register is erased (all 0s), the entire memory is
accessible for program and erase. When bits within the register are
programmed, they lock blocks of memory address ranges as shown in
5.9 FLASH Block Protect
be erased or programmed only with an external voltage V
the IRQ pin. The presence of V
monitor mode out of reset. Therefore, the ability to change the block
protect register is voltage dependent and can occur in either user or
monitor modes.
Figure 5-2
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is always required when programming any part of the
FLASH-2 Memory
Register. The block protect register itself can
HI
on the IRQ pin also allows entry into
MC68HC908AS60 — Rev. 1.0
5.6 FLASH Erase
HI
present on