MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 341

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.5.2.8 Break (BREAK)
21.5.2.9 Idle Bus (IDLE)
21.5.3 J1850 VPW Symbols
MC68HC908AS60 — Rev. 1.0
NOTE:
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats the
BREAK as if a transmission error had occurred and halts transmission.
If the BDLC detects a BREAK symbol while receiving a message, it
treats the BREAK as a reception error and sets the invalid symbol flag in
the BSVR, also ignoring the frame it was receiving. If while receiving a
message in 4X mode, the BDLC detects a BREAK symbol, it treats the
BREAK as a reception error, sets the invalid symbol flag, and exits 4X
mode (for example, the RX4XE bit in BCR2 is cleared automatically). If
bus control is required after the BREAK symbol is received and the IFS
time has elapsed, the programmer must resend the transmission byte
using highest priority.
The J1850 protocol BREAK symbol is not related to the M68HC08 break
module (see
An idle condition exists on the bus during any passive period after
expiration of the IFS period (for example,
an idle bus condition can begin transmission immediately.
Huntsinger’s variable pulse-width modulation (VPW) is an encoding
technique in which each bit is defined by the time between successive
transitions and by the level of the bus between transitions (for instance,
active or passive). Active and passive bits are used alternately. This
encoding technique is used to reduce the number of bus transitions for
a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either
the active or passive level and one of two lengths, either 64 s or 128 s
(t
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame
NOM
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
at 10.4 kbps baud rate), depending on the encoding of the
Go to: www.freescale.com
Section 12. Break
Module).
Byte Data Link Controller-Digital (BDLC-D)
300 s). Any node sensing
BDLC MUX Interface
Technical Data