MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 331

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.4.1 BDLC Operating Modes
21.4.1.1 Power Off Mode
MC68HC908AS60 — Rev. 1.0
$003B
$003C
$003D
$003E
$003F
Addr.
BDLC Analog and Roundtrip
BDLC State Vector Register
BDLC Control Register 1
BDLC Control Register 2
Delay Register (BARD)
BDLC Data Register
Register Name
See page 358.
See page 359.
See page 362.
See page 370.
See page 372.
(BSVR)
(BCR1)
(BCR2)
The BDLC has five main modes of operation which interact with the
power supplies, pins, and rest of the MCU as shown in
For the BDLC to guarantee operation, this mode is entered from reset
mode whenever the BDLC supply voltage, V
minimum specified value. The BDLC will be placed in reset mode by
low-voltage reset (LVR) before being powered down. In power off mode,
the pin input and output specifications are not guaranteed.
(BDR)
Figure 21-2. BDLC I/O Register Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Byte Data Link Controller-Digital (BDLC-D)
ALOOP
IMSG
Bit 7
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ATE
BD7
1
1
1
0
0
= Unimplemented
DLOOP
RXPOL
CLKS
BD6
6
1
1
1
0
0
RX4XE
BD5
R1
I3
5
0
0
1
0
0
Indeterminate after reset
NBFS
BD4
Byte Data Link Controller-Digital (BDLC-D)
R0
I2
R
4
0
0
0
0
0
= Reserved
TEOD
BO3
BD3
R
I1
DD
3
0
0
0
0
0
, drops below its
TSIFR
BO2
BD2
I0
R
2
1
0
0
0
0
Functional Description
Figure
TMIFR1
BO1
BD1
Technical Data
IE
1
1
0
0
0
0
21-3.
TMIFR0
WCM
Bit 0
BO0
BD0
1
0
0
0
0