MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 160

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
.
VRS
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f
is equal to the nominal center-of-range
VRS
frequency, f
, (4.9152 MHz) times a linear factor L or (L)f
.
NOM
NOM
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
, and is fed to the PLL through a
RCLK
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency f
= f
.
RDV
RCLK
The VCO’s output clock, CGMVCLK, running at a frequency f
, is fed
VCLK
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency f
= f
/N. See
VDV
VCLK
10.4.2.4 Programming the PLL
for more information.
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the dc voltage on the external capacitor connected to
CGMXFC based on the width and direction of the correction pulse. The
filter can make fast or slow corrections depending on its mode, as
described in
10.4.2.2 Acquisition and Tracking
Modes. The value of
the external capacitor and the reference frequency determines the
speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f
. The circuit determines the mode of the PLL and the lock
RDV
condition based on this comparison.
Technical Data
MC68HC908AS60 — Rev. 1.0
Clock Generator Module (CGM)
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