MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 399

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MC68HC908AS60 — Rev. 1.0
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMA
counter registers matches the value in the TIMA channel x registers.
When CHxIE = 0, clear CHxF by reading TIMA channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMA channel 0, TIMA channel 2, and TIMA
channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TACH1 pin to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TACH3 pin to general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and
reverts TACH5 pin to general-purpose I/O.
Reset clears the MSxB bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
Timer Interface Module A (TIMA-6)
Go to: www.freescale.com
Timer Interface Module A (TIMA-6)
Technical Data
I/O Registers