MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 360

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller-Digital (BDLC-D)
Technical Data
IMSG — Ignore Message Bit
CLKS — Clock Bit
R1 and R0 — Rate Select Bits
This bit is used to disable the receiver until a new start-of-frame (SOF)
is detected.
For J1850 bus communications to take place, the nominal BDLC
operating frequency (f
The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to automatically adjust symbol timing.
These bits determine the amount by which the frequency of the MCU
CGMXCLK signal is divided to form the MUX interface clock (f
which defines the basic timing resolution of the MUX interface. They
may be written only once after reset, after which they become
read-only bits.
The nominal frequency of f
1.0 MHz for J1850 bus communications to take place. Hence, the
value programmed into these bits is dependent on the chosen MCU
system clock frequency per
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Disable receiver. When set, all BDLC interrupt requests will be
0 = Enable receiver. This bit is cleared automatically by the
1 = Binary frequency (1.048576 MHz) selected for f
0 = Integer frequency (1 MHz) selected for f
Byte Data Link Controller-Digital (BDLC-D)
masked (except $20 in BSVR) and the status bits will be held
in their reset state. If this bit is set while the BDLC is receiving
a message, the rest of the incoming message will be ignored.
reception of an SOF symbol or a BREAK symbol. It will then
generate interrupt requests and will allow changes of the
status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit.
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BDLC
) must always be 1.048576 MHz or 1 MHz.
BDLC
Table
must always be 1.048576 MHz or
21-3.
MC68HC908AS60 — Rev. 1.0
BDLC
BDLC
BDLC
)