MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 321

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MC68HC908AS60CFN

Manufacturer Part Number
MC68HC908AS60CFN
Description
IC MCU 60K FLASH 8MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908AS60CFN

Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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20.9.2 Data Direction Register G
MC68HC908AS60 — Rev. 1.0
NOTE:
Address:
PTG[2:0] — Port G Data Bits
Data direction register G (DDRG) determines whether each port G pin is
an input or an output. Writing a logic 1 to a DDRG bit enables the output
buffer for the corresponding port G pin; a logic 0 disables the output
buffer.
DDRG[2:0] — Data Direction Register G Bits
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 20-22
Reset:
Read:
Write:
These read/write bits are software programmable. Data direction of
each port G pin is under the control of the corresponding bit in data
direction register G. Reset has no effect on PTG[2:0].
These read/write bits control port G data direction. Reset clears
DDRG[2:0], configuring all port G pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
$000E
Bit 7
Figure 20-21. Data Direction Register G (DDRG)
R
R
0
0
Go to: www.freescale.com
shows the port G I/O logic.
Input/Output (I/O) Ports
= Reserved
R
6
0
0
R
5
0
0
R
4
0
0
R
3
0
0
DDRG2
2
0
Input/Output (I/O) Ports
DDRG1
1
0
Technical Data
DDRG0
Port G
Bit 0
0

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