MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 364

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MC68HC908AS60CFN

Manufacturer Part Number
MC68HC908AS60CFN
Description
IC MCU 60K FLASH 8MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908AS60CFN

Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Byte Data Link Controller-Digital (BDLC-D)
Technical Data
NBFS — Normalization Bit Format Select Bit
TEOD — Transmit End-of-Data Bit
This bit controls the format of the normalization bit (NB)
(see
long (logic 0) for in-frame responses containing cyclical redundancy
check (CRC) and an active short (logic 1) for in-frame responses
without CRC.
This bit is set by the programmer to indicate the end of a message is
being sent by the BDLC. It will append an 8-bit CRC after completing
transmission of the current byte. This bit also is used to end an
in-frame response (IFR). If the transmit shadow register is full when
TEOD is set, the CRC byte will be transmitted after the current byte in
the Tx shift register and the byte in the Tx shadow register have been
transmitted. (See
description of the transmit shadow register.) Once TEOD is set, the
transmit data register empty flag (TDRE) in the BDLC state vector
register (BSVR) is cleared to allow lower priority interrupts to occur.
(See
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = NB that is received or transmitted is a 0 when the response part
0 = NB that is received or transmitted is a 1 when the response part
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of
Byte Data Link Controller-Digital (BDLC-D)
Figure
21.7.4 BDLC State Vector
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
the first CRC bit that is sent or if an error is detected. When
TEOD is used to end an IFR transmission, TEOD is cleared
when the BDLC receives back a valid EOD symbol or an error
condition occurs.
Go to: www.freescale.com
21-19). SAE J1850 strongly encourages using an active
21.6.3 Rx and Tx Shadow Registers
Register.)
MC68HC908AS60 — Rev. 1.0
for a

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