MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 392

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer Interface Module A (TIMA-6)
22.8.1 TIMA Clock Pin (PTD6/ATD14/TCLK)
22.8.2 TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0)
22.9 I/O Registers
Technical Data
PTD6/TACLK is an external clock input that can be the clock source for
the TIMA counter instead of the prescaled internal bus clock. Select the
PTD6/TACLK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See
minimum TCLK pulse width, TCLK
The maximum TCLK frequency is the least: 4 MHz or bus frequency 2.
PTD6/TACLK is available as a general-purpose I/O pin or ADC channel
when not used as the TIMA clock input. When the PTD6/TACLK pin is
the TIMA clock input, it is an input regardless of the state of the DDRD6
bit in data direction register D.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE2/TACH0, PTE6/TACH2, and
PTF2 can be configured as buffered output compare or buffered PWM
pins.
These I/O registers control and monitor TIMA operation:
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Freescale Semiconductor, Inc.
For More Information On This Product,
TIMA status and control register (TASC)
TIMA control registers (TACNTH–TACNTL)
TIMA counter modulo registers (TAMODH–TAMODL)
TIMA channel status and control registers (TASC0, TASC1,
TASC2, TASC3, TASC4, and TSAC5)
TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L,
TACH2H–TACH2L, TACH3H–TACH3L, TACH4H–TACH4L, and
TACH5H–TACH5L)
Timer Interface Module A (TIMA-6)
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22.9.1 TIMA Status and Control
------------------------------------ -
bus frequency
1
LMIN
or TCLK
+
t
SU
MC68HC908AS60 — Rev. 1.0
HMIN
Register.) The
, is: