MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 312

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Input/Output (I/O) Ports
20.6.2 Data Direction Register D
Technical Data
NOTE:
NOTE:
NOTE:
Address:
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the ADC. However, the DDRD bits
always determine whether reading port D returns the states of the
latches or logic 0.
TACLK — Timer Clock Input Bit
Do not use ADC channel ATD14 when using the PTD6/TACLK pin as the
clock input for the TIMA.
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
DDRD[7:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Reset:
Read:
Write:
The PTD6/TACLK pin is the external clock input for the TIMA. The
prescaler select bits, PS[2:0], select PTD6/TACLK as the TIMA clock
input. (See
selected as the TIMA clock, PTD6/TACLK is available for
general-purpose I/O or as an ADC channel.
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
DDRD7
$0007
Bit 7
Figure 20-12. Data Direction Register D (DDRD)
0
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Input/Output (I/O) Ports
22.9.1 TIMA Status and Control
DDRD6
6
0
DDRD5
5
0
DDRD4
4
0
DDRD3
3
0
MC68HC908AS60 — Rev. 1.0
Register.) When not
DDRD2
2
0
DDRD1
1
0
DDRD0
Bit 0
0