MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 333

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.4.1.3 Run Mode
21.4.1.4 Wait Mode
21.4.1.5 Stop Mode
MC68HC908AS60 — Rev. 1.0
This mode is entered from reset mode after all MCU reset sources are
no longer asserted. Run mode is entered from the BDLC wait mode
whenever activity is sensed on the J1850 bus.
Run mode is entered from the BDLC stop mode whenever network
activity is sensed, although messages will not be received properly until
the clocks have stabilized and the CPU is also in run mode.
In this mode, normal network operation takes place. The user should
ensure that all BDLC transmissions have ceased before exiting this
mode.
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and if the WCM bit in the
BCR1 register is cleared previously.
In this mode, the BDLC internal clocks continue to run. The first
passive-to-active transition of the bus generates a CPU interrupt request
from the BDLC, which wakes up the BDLC and the CPU. In addition, if
the BDLC receives a valid end-of-frame (EOF) symbol while operating in
wait mode, then the BDLC also will generate a CPU interrupt request,
which wakes up the BDLC and the CPU. See
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BCR1 is set previously.
In this mode, the BDLC internal clocks are stopped but the physical
interface circuitry is placed in a low-power mode and awaits network
activity. If network activity is sensed, then a CPU interrupt request will be
generated, restarting the BDLC internal clocks. See
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
Go to: www.freescale.com
Byte Data Link Controller-Digital (BDLC-D)
21.8.1 Wait
21.8.2 Stop
Functional Description
Mode.
Technical Data
Mode.