MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 78

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FLASH-2 Memory
5.3 Functional Description
Technical Data
The FLASH-2 memory is an array of up to 29,616 bytes. An erased bit
reads as a logic 0 and a programmed bit reads as a logic 1. Program and
erase operations are facilitated through control bits in a memory mapped
register. Details for these operations appear later in this section. Memory
in the FLASH array is organized into pages within rows. There are eight
pages of memory per row with eight bytes per page. The minimum erase
block size is a single row, 64 bytes. Programming is performed on a
per-page basis, eight bytes at a time.
The address ranges for the user memory and the control register are:
When programming the FLASH, just enough program time must be used
to program a page. Too much program time can result in a program
disturb condition, in which case an erased bit on the row being
programmed becomes unintentionally programmed. Program disturb is
avoided by using an iterative program and margin read technique known
as the smart programming algorithm. The smart programming algorithm
is required whenever programming the FLASH. See
Program/Margin Read
To avoid the program disturb issue, each storage page of the row should
not be programmed more than once before it is erased. The eight
program cycle maximum per row aligns with the architecture’s eight
pages of storage per row. The margin read step of the smart
programming algorithm is used to ensure programmed bits are
programmed to sufficient margin for data retention over the device
lifetime.
The row architecture for this array is:
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Freescale Semiconductor, Inc.
For More Information On This Product,
$0450–$05FF
$0E00–$7FFF
$FE11, FLASH-2 control register
$7F40–$7F7F (Row 509)
$7F80–$7FBF (Row 510)
$7FC0–$7FFF (Row 511)
Go to: www.freescale.com
FLASH-2 Memory
Operation.
MC68HC908AS60 — Rev. 1.0
5.7 FLASH