MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 174

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Clock Generator Module (CGM)
10.7 Interrupts
Technical Data
NOTE:
VRS7–VRS4 — VCO Range Select Bits
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupt requests from the PLL. PLLF, the interrupt flag in the
PCTL, becomes set whether CPU interrupt requests are enabled or not.
When the AUTO bit is clear, CPU interrupt requests from the PLL are
disabled and PLLF reads as logic 0.
Software should read the LOCK bit after a PLL CPU interrupt request to
see if the request was due to an entry into lock or an exit from lock. When
the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
CPU interrupt requests should be disabled to prevent PLL interrupt
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency,
f
10.6.1 PLL Control
the PLLON bit in the PLL control register (PCTL) is set. See
Special Programming
select bits disables the PLL and clears the BCS bit in the PCTL. (See
10.4.3 Base Clock Selector Circuit
Programming Exceptions
the bits to $6 to give a default range multiply value of 6.
Freescale Semiconductor, Inc.
VRS
For More Information On This Product,
. (See
Clock Generator Module (CGM)
Go to: www.freescale.com
10.4.2.1
Circuits,
Register.) VRS7–VRS4 cannot be written when
Exceptions. A value of $0 in the VCO range
for more information.) Reset initializes
10.4.2.4 Programming the
and
10.4.2.5 Special
MC68HC908AS60 — Rev. 1.0
PLL, and
10.4.2.5