MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 345

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.5.4 J1850 VPW Valid/Invalid Bits and Symbols
21.5.4.1 Invalid Passive Bit
21.5.4.2 Valid Passive Logic 0
MC68HC908AS60 — Rev. 1.0
The timing tolerances for receiving data bits and symbols from the J1850
bus have been defined to allow for variations in oscillator frequencies. In
many cases, the maximum time allowed to define a data bit or symbol is
equal to the minimum time allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol
is being received is equal to a single period of the MUX interface clock
(t
concurrences equals one cycle of t
This one clock resolution allows the BDLC to differentiate properly
between the different bits and symbols. This is done without reducing the
valid window for receiving bits and symbols from transmitters onto the
J1850 bus, which has varying oscillator frequencies.
In Huntsinger’s variable pulse width (VPW) modulation bit encoding, the
tolerances for both the passive and active data bits received and the
symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the
minimum length of a passive logic 1, and the maximum length of an
active logic 0 is equal to the minimum length of a valid SOF symbol.
See
beginning the next data bit or symbol occurs between the
active-to-passive transition beginning the current data bit (or symbol)
and a, the current bit would be invalid.
See
beginning the next data bit (or symbol) occurs between a and b, the
current bit would be considered a logic 0.
BDLC
Freescale Semiconductor, Inc.
Figure 21-8
Figure 21-8
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Byte Data Link Controller-Digital (BDLC-D)
), an apparent separation in these maximum time/minimum time
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(1). If the passive-to-active received transition
(2). If the passive-to-active received transition
BDLC
Byte Data Link Controller-Digital (BDLC-D)
.
BDLC MUX Interface
Technical Data