UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 974

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(23) CAN0 message control register m (C0MCTRLm)
(a) Read
(b) Write
(a) Read
Remark The MOW bit is not set to 1 even if a remote frame is received and stored in the transmit message
Note
The C0MCTRLm register is used to control the operation of the message buffer.
After reset: 00x000000
C0MCTRLm
C0MCTRLm
MUC
MOW
0
1
0
1
DN
IE
0
1
0
1
Note
The MUC bit is undefined until the first reception and storage is performed.
buffer with the DN bit = 1.
The CAN module is not updating the message buffer (reception and storage).
The CAN module is updating the message buffer (reception and storage).
The message buffer is not overwritten by a newly received data frame.
The message buffer is overwritten by a newly received data frame.
000xx000B
Receive message buffer: Valid message reception completion interrupt disabled.
Transmit message buffer: Normal message transmission completion interrupt disabled.
Receive message buffer: Valid message reception completion interrupt enabled.
Transmit message buffer: Normal message transmission completion interrupt enabled.
A data frame or remote frame is not stored in the message buffer.
A data frame or remote frame is stored in the message buffer.
15
15
0
7
0
0
7
0
R/W
14
14
0
6
0
0
6
0
Bit indicating that message buffer data is being updated
Address: See Table 20-16.
Message buffer interrupt request enable bit
MUC
13
13
5
0
0
5
0
Message buffer overwrite status bit
Message buffer data update bit
MOW
MOW
Clear
12
12
0
4
0
4
Clear
Set
11
11
IE
IE
IE
0
3
3
CHAPTER 20 CAN CONTROLLER
Clear
DN
DN
10
10
0
2
0
2
Clear
TRQ
TRQ
TRQ
Set
9
0
1
9
1
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Clear
RDY
RDY
RDY
Set
8
0
0
8
0
(1/3)