UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 77

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
3.4.6
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Notes 1
FFFFF004H
FFFFF006H
FFFFF008H
FFFFF00AH
FFFFF00CH
FFFFF024H
FFFFF026H
FFFFF028H
FFFFF02AH
FFFFF02CH
FFFFF044H
FFFFF046H
FFFFF048H
FFFFF04AH
FFFFF04CH
FFFFF064H
FFFFF066H
FFFFF06EH
FFFFF080H
FFFFF082H
FFFFF084H
FFFFF086H
FFFFF088H
FFFFF08AH
FFFFF08CH
FFFFF08EH
FFFFF090H
FFFFF092H
FFFFF094H
FFFFF096H
FFFFF098H
FFFFF09AH
FFFFF09CH
FFFFF004H
FFFFF005H
FFFFF024H
FFFFF025H
FFFFF044H
FFFFF045H
Address
Peripheral I/O registers
2. V850ES/JH3-H only
3.
The output latch is 00H or 0000H. When these registers are in the input mode, the pin statuses are read.
μ
PD70F3770, 70F3771 only
Port DL register
Port DL register L
Port DL register H
Port DH register
Port CS register
Port CT register
Port CM register
Port DL mode register
Port DL mode register L
Port DL mode register H
Port DH mode register
Port CS mode register
Port CT mode register
Port CM mode register
Port DL mode control register
Port DL mode control register L
Port DL mode control register H
Port DH mode control register
Port CS mode control register
Port CT mode control register
Port CM mode control register
Peripheral I/O area select control register
Bus size configuration register
System wait control register
DMA source address register 0L
DMA source address register 0H
DMA destination address register 0L
DMA destination address register 0H
DMA source address register 1L
DMA source address register 1H
DMA destination address register 1L
DMA destination address register 1H
DMA source address register 2L
DMA source address register 2H
DMA destination address register 2L
DMA destination address register 2H
DMA source address register 3L
DMA source address register 3H
DMA destination address register 3L
Function Register Name
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 3
PMCDH
PMCCS
PDL
PDLL
PDLH
PDH
PCS
PCT
PCM
PMDL
PMDLL
PMDLH
PMDH
PMCS
PMCT
PMCM
PMCDL
PMCDLL
PMCDLH
PMCCT
PMCCM
BPC
BSC
VSWC
DSA0L
DSA0H
DDA0L
DDA0H
DSA1L
DSA1H
DDA1L
DDA1H
DSA2L
DSA2H
DDA2L
DDA2H
DSA3L
DSA3H
DDA3L
Symbol
Note 3
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
R/W
R/W
CHAPTER 3 CPU FUNCTION
Manipulatable Bits
1
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Page 77 of 1509
0000H
00H
00H
00H
00H
00H
00H
FFFFH
FFH
FFH
FFH
FFH
FFH
FFH
0000H
00H
00H
00H
00H
00H
00H
0000H
5555H
77H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Default Value
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
(1/14)