UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1002

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
20.12 Interrupt Function
are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt
sources is generated, the interrupt sources can be identified by using an interrupt status register. After an interrupt source
has occurred, the corresponding interrupt status bit must be cleared to 0 by software.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
1
2
3
4
5
6
No.
The CAN module provides 6 different interrupt sources.
The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals
Remark
Notes 1. The C0MCTRL.IE bit (message buffer interrupt enable bit) of the corresponding message buffer has to be
CINTS0
CINTS1
CINTS2
CINTS3
CINTS4
CINTS5
Name
Interrupt Status Bit
2.
3.
4.
m = 00 to 31
Note 1
Note 1
set to 1 for that message buffer to participate in the interrupt generation process.
This interrupt is generated when the transmission/reception error counter is at the warning level, or in the
error passive or bus-off state.
This interrupt is generated when a stuff error, form error, ACK error, bit error, or CRC error occurs.
This interrupt is generated when the CAN module is woken up from the CAN sleep mode because a falling
edge is detected at the CAN reception pin (CAN bus transition from recessive to dominant).
C0INTS
C0INTS
C0INTS
C0INTS
C0INTS
C0INTS
Register
CIE0
CIE1
CIE2
CIE3
CIE4
CIE5
Interrupt Enable Bit
Name
Table 20-20. List of CAN Module Interrupt Sources
Note 1
Note 1
C0IE
C0IE
C0IE
C0IE
C0IE
C0IE
Register
Request Signal
INTC0TRX
INTC0REC
INTC0ERR
INTC0WUP
Interrupt
Message frame successfully transmitted from
message buffer m
Valid message frame reception in message buffer m
CAN module error state interrupt
CAN module protocol error interrupt
CAN module arbitration loss interrupt
CAN module wakeup interrupt from CAN sleep
mode
Note 4
CHAPTER 20 CAN CONTROLLER
Interrupt Source Description
Note 2
Note 3
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