UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1341
UPD70F3765GF-GAT-AX
Manufacturer Part Number
UPD70F3765GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3765GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3765GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(3) Operation in STOP mode or after STOP mode is released
(4) Operation when main clock is stopped (arbitrary)
(5) Operation while CPU is operating on internal oscillation clock (CCLS.CCLSF bit = 1)
Internal oscillation
Internal oscillation
If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while
the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is
automatically started.
During subclock operation (PCC.CLS bit = 1) or when the main clock is stopped by setting the PCC.MCK bit to 1,
the monitor operation is stopped until the main clock operation is started (PCC.CLS bit = 0). The monitor operation
is automatically started when the main clock operation is started.
The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1.
Clock monitor
Clock monitor
Main clock
Main clock
operation
operation
CLME
CLME
status
status
clock
clock
CPU
CPU
Figure 27-4. Operation in STOP Mode or After STOP Mode Is Released
operation
Normal
monitor
Figure 27-5. Operation When Main Clock Is Stopped (Arbitrary)
monitor
During
During
PCC.MCK bit = 1
Oscillation stops
Oscillation stops
Monitor stops
STOP
Subclock operation
Oscillation stabilization time
Monitor stops
Oscillation stabilization time
Oscillation stabilization time
Oscillation stabilization
time count by software
(set by OSTS register)
(set by OSTS register)
Monitor stops
CHAPTER 27 CLOCK MONITOR
Main clock operation
Normal operation
During monitor
During monitor
Page 1341 of 1509
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