UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 552

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
Caution The 16-bit counter is cleared to 0000H when the clear level condition of the TT0ZCL, TT0BCL, and
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
TT0ZCL Bit
(b) Clearing method <2>: By detecting clear level condition of the TENC00, TENC01, and TECR0 pins
TT0ACL bits match the input level of the TECR0, TENC01, or TENC00 pin.
(TT0SCE bit = 1)
0
0
0
0
1
1
1
1
When the TT0SCE bit = 1, the 16-bit counter is cleared to 0000H if the clear level condition of the TECR0,
TENC00, or TENC01 pin specified by the TT0ZCL, TT0BCL, and TT0ACL bits is detected. At this time, the
encoder clear interrupt request signal (INTTT0EC) is not generated. The settings of the TT0ECS1 and
TT0ECS0 bits is invalid when the TT0SCE bit = 1.
Clear Level Condition Setting
Table 9-10. 16-bit Counter Clearing Condition When TT0SCE Bit = 1
TT0BCL Bit
0
0
1
1
0
0
1
1
TT0ACL Bit
0
1
0
1
0
1
0
1
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
TECR0 Pin
H
H
H
H
L
L
L
L
Input Level of Encoder Pin
TENC01 Pin
H
H
H
H
L
L
L
L
TENC00 Pin
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H
H
H
H
L
L
L
L