UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 839

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
19.6.2 Addresses
connected to the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
data values stored in the SVAn register. If the address data matches the values of the SVAn register, the slave device is
selected and communicates with the master device until the master device generates a start condition or stop condition (n
= 0 to 2).
specification are written together to the IICn registers as eight bits of data. Received addresses are written to the IICn
register (n = 0 to 2).
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The 7 bits of data that follow the start condition are defined as an address.
An address is a 7-bit data segment that is output so that the master device can select one of the slave devices that are
The slave devices detect via hardware the start condition and check whether or not the 7-bit address data matches the
An address is output when the slave address and the transfer direction described in 19.6.3
The slave address is assigned to the higher 7 bits of the IICn register.
Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received
Remark
during slave device operation.
n = 0 to 2
INTIICn
SDA0n
SCL0n
AD6
1
AD5
2
Figure 19-9. Address
AD4
3
Address
AD3
4
AD2
5
AD1
6
AD0
7
R/W
8
9
CHAPTER 19 I
Note
Transfer direction
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C BUS