UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 30

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
1.6.2
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) CPU
(2) Bus control unit (BCU)
(3) Flash memory (ROM)
(4) RAM
(5) Interrupt controller (INTC)
(6) Clock generator (CG)
(7) Internal oscillator
(8) Timer/counter
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits)
contribute to faster complex processing.
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU
generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an
instruction queue.
This is a 512/384/256 KB flash memory mapped to addresses 0000000H to 007FFFFH/0000000H to
005FFFFH/0000000H to 003FFFFH. It can be accessed from the CPU in one clock during instruction fetch.
This is a 48/40/32 KB RAM mapped to addresses 3FF3000H to 3FFEFFFH/3FF5000H to 3FFEFFFH/3FF7000H to
3FFEFFFH. It can be accessed from the CPU in one clock during data access. An 8 KB data-only RAM is
incorporated at addresses 00280000H to 002FFFFFH.
This controller handles hardware interrupt requests (NMI, INTP0 to INTP18) from on-chip peripheral hardware and
external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed
servicing control can be performed.
A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (f
and subclock frequency (f
clock frequency (f
The CPU clock frequency (f
An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP). The internal oscillator
supplies the clock for watchdog timer 2 and timer M.
Six-channel 16-bit timer/event counter AA (TAA), two-channel 16-bit timer/event counter AB (TAB), one-channel 16-
bit timer/event counter T (TMT), and four-channel 16-bit interval timer M (TMM) are provided on chip. The motor
control function can be realized using TAB1 and TAA4 in combination.
Internal units
XX
) as is. In the PLL mode, f
XT
CPU
), respectively. There are two modes: In the clock-through mode, f
) can be selected from among f
X
is used multiplied by 8.
XX
, f
XX
/2, f
XX
/4, f
XX
CHAPTER 1 INTRODUCTION
/8, f
XX
/16, f
XX
/32, and f
X
is used as the main
Page 30 of 1509
XT
.
X
)