UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1324

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
25.7 Subclock Operation Mode
25.7.1 Setting and operation status
Check whether the clock has been switched by using the PCC.CLS bit.
operates only on the subclock.
mode because the subclock is used as the internal system clock. In addition, the power consumption can be further
reduced to the level of the STOP mode by stopping the operation of the main clock oscillator.
25.7.2 Releasing subclock operation mode
detector (LVI), or clock monitor (CLM)) when the CK3 bit is set to 0.
clock by software, and set the CK3 bit to 0.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode.
When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock.
When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped. As a result, the system
In the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation
Table 25-10 shows the operating status in subclock operation mode.
Cautions 1. When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to PCC.CK0 bits
Remark Internal system clock (f
The subclock operation mode is released by a reset signal (reset by RESET pin input, WDT2RES signal, low-voltage
If the main clock is stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main
The normal operation mode is restored when the subclock operation mode is released.
Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are
manipulation instruction to manipulate the bit is recommended).
For details of the PCC register, see 6.3 (1) Processor clock control register (PCC).
(using a bit manipulation instruction to manipulate the bit is recommended). For details of the
PCC register, see 6.3 (1) Processor clock control register (PCC).
satisfied and set the subclock operation mode.
Internal system clock (f
CLK
): Clock generated from main clock (f
CK2 to CK0 bits
CLK
) > Subclock (f
XT
= 32.768 kHz) × 4
CHAPTER 25 STANDBY FUNCTION
XX
) in accordance with the settings of the
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