UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 287

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
and TOAAn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TAAnCCRm
register, a compare match interrupt request signal (INTTAAnCCm) is generated, and the output signal of the TOAAnm pin
is inverted.
generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR
instruction by software.
that time, and compared with the count value.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TAAnCE bit is set to 1, 16-bit timer/event counter AA starts counting, and the output signals of the TOAAn0
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
The TAAnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
INTTAAnCC0 signal
INTTAAnCC1 signal
TAAnCCR1 register
Remark
TAAnCCR0 register
TOAAn0 pin output
TOAAn1 pin output
INTTAAnOV signal
16-bit counter
TAAnOVF bit
TAAnCE bit
Figure 7-34. Basic Timing in Free-Running Timer Mode (Compare Function)
n = 0 to 3, 5
m = 0, 1
FFFFH
0000H
D
10
D
00
D
CLR instruction
Cleared to 0 by
10
D
00
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
D
10
D
00
Cleared to 0 by
CLR instruction
D
11
D
01
CLR instruction
Cleared to 0 by
D
11
D
D
D
01
01
11
CLR instruction
Cleared to 0 by
D
11
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