UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 354

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
TABnIOC0
By reading the TABnCNT register, the count value of the 16-bit counter can be read.
If the TABnCCR0 register is set to D
Interval = (D
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode. However, the set
Therefore, mask the interrupt requests by using the corresponding interrupt mask flags (TABnCCMK1 to
(c) TABn I/O control register 0 (TABnIOC0)
(d) TABn counter read buffer register (TABnCNT)
(e) TABn capture/compare register 0 (TABnCCR0)
(f) TABn capture/compare registers 1 to 3 (TABnCCR1 to TABnCCR3)
value of the TABnCCR1 to TABnCCR3 registers is transferred to the CCR1 to CCR3 buffer
registers. The compare match interrupt request signals (INTTABnCCR1 to INTTABnCCR3) are
generated when the count value of the 16-bit counter matches the value of the CCR1 to CCR3
buffer registers.
TABnCCMK3).
Remarks 1. TABn I/O control register 1 (TABnIOC1), TABn I/O control register 2 (TABnIOC2), and
TABnOL3
0
0/1
+ 1) × Count clock cycle
2. n = 0, 1
TABnOE3 TABnOL2 TABnOE2
Figure 8-4. Register Setting for Interval Timer Mode Operation (2/2)
TABn option register 0 (TABnOPT0) are not used in the interval timer mode.
0/1
0/1
0
, the interval is as follows.
0/1
TABnOL1
0/1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
TABnOE1 TABnOL0 TABnOE0
0/1
0/1
0/1
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level with
operation of TOABn0 pin disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Setting of output level with
operation of TOABn1 pin disabled
0: Low level
1: High level
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Setting of output level with
operation of TOABn3 pin disabled
0: Low level
1: High level
Setting of output level with
operation of TOABn2 pin disabled
0: Low level
1: High level
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