UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 881

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UPD70F3765GF-GAT-AX

Manufacturer Part Number
UPD70F3765GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet

Specifications of UPD70F3765GF-GAT-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3765GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Remarks 1. For the transmission and reception formats, comply with the specifications of the communicating
2. When using the V850ES/JG3-H or V850ES/JH3-H as the master in a multimaster system, read the
3. When using the V850ES/JG3-H or V850ES/JH3-H as the slave in a multimaster system, confirm the
4. n = 0 to 2
product.
IICSn.MSTSn bit for each INTIICn interrupt occurrence to confirm the arbitration result.
status using the IICSn and IICFn registers for each INTIICn interrupt occurrence to determine the
next processing.
No
No
EXCn = 1 or COIn = 1?
Not in communication
Transfer completed?
interrupt occurred?
interrupt occurred?
Figure 19-19. Master Operation in Multimaster System (3/3)
MSTSn = 1?
ACKDn = 1?
MSTSn = 1?
ACKDn = 1?
TRCn = 1?
WTIMn = 1
Restarted?
Write IICn
Write IICn
STTn = 1
INTIICn
INTIICn
C
C
2
1
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
Communication start
(address, transfer direction specification)
Transmission start
Waiting for ACK detection
Waiting for data transmission
Slave operation
SPTn = 1
END
2
2
WTIMn = WRELn = 1
Transfer completed?
interrupt occurred?
interrupt occurred?
MSTSn = 1?
MSTSn = 1?
WRELn = 1
ACKEn = 1
WTIMn = 0
ACKEn = 0
Read IICn
INTIICn
INTIICn
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Waiting for ACK detection
Reception start
Waiting for data
transmission
CHAPTER 19 I
2
2
Page 881 of 1509
2
C BUS

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