UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 263

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
<1> Count operation start flow
<2> TAAnCCR0 and TAAnCCR1 register
(TAAnCKS0 to TAAnCKS2 bits),
setting change flow
Setting of TAAnCCR0 register
Setting of TAAnCCR1 register
Register initial setting
TAAnCCR0 register,
TAAnCTL1 register,
TAAnIOC0 register,
TAAnIOC2 register,
TAAnCCR1 register
TAAnCTL0 register
Remark
TAAnCE bit = 1
START
Figure 7-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
n = 0 to 3, 5
m = 0, 1
The TAAnCKS0 to
TAAnCKS2 bits can be
set at the same time
when counting is enabled
(TAAnCE bit = 1).
Trigger wait status
Initial setting of these
registers is performed
before setting the
TAAnCE bit to 1.
TAAnCCR1 register write
processing is necessary
only when the set
cycle is changed.
When the counter is
cleared after setting,
the values of the
TAAnCCRm register are
transferred to the CCRm
buffer register in a batch.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
<3> TAAnCCR0, TAAnCCR1 register
<4> TAAnCCR0, TAAnCCR1 register
<5> Count operation stop flow
Setting of TAAnCCR1 register
Setting of TAAnCCR0 register
Setting of TAAnCCR1 register
setting change flow
setting change flow
TAAnCE bit = 0
STOP
Counting is stopped.
Only writing of the TAAnCCR1
register must be performed when
When the counter is cleared after
setting, the value of the
TAAnCCRm register is transferred
to the CCRm buffer register.
When the counter is
cleared after setting,
the values of the TAAnCCRm
register are transferred to
the CCRm buffer register
in a batch.
the set duty factor is changed.
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