UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 261
UPD70F3765GF-GAT-AX
Manufacturer Part Number
UPD70F3765GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3765GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3765GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
TAAnIOC2
(d) TAAn I/O control register 2 (TAAnIOC2)
(e) TAAn counter read buffer register (TAAnCNT)
(f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
If D
the PWM waveform are as follows.
Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are
Cycle = (D
Active level width = D
0
is set to the TAAnCCR0 register and D
0
Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (2/2)
2. n = 0 to 3, 5
0
not used in the external trigger pulse output mode.
+ 1) × Count clock cycle
0
0
1
× Count clock cycle
0
TAAnEES1 TAAnEES0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
0
1
to the TAAnCCR1 register, the cycle and active level of
0
TAAnETS1 TAAnETS0
0/1
0/1
Select valid edge of
external trigger input
Page 261 of 1509
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