UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 278

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
PWM waveform from the TOAAn1 pin.
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the value of
the CCR1 buffer register.
counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TAAnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The PWM waveform can be changed by rewriting the TAAnCCRm register while the counter is operating. The newly
The compare match interrupt request signal INTTAAnCC0 is generated the next time the 16-bit counter counts after its
The value set to the TAAnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
Remark
Active level width = (Set value of TAAnCCR1 register) × Count clock cycle
Cycle = (Set value of TAAnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1)
n = 0 to 3, 5
m = 0, 1
CCR0 buffer register
CCR1 buffer register
INTTAAnCC0 signal
INTTAAnCC1 signal
TAAnCCR0 register
TAAnCCR1 register
TOAAn0 pin output
TOAAn1 pin output
16-bit counter
TAAnCE bit
FFFFH
0000H
Figure 7-30. Basic Timing in PWM Output Mode
Active period
D
(D
10
D
10
00
)
(D
D
D
Cycle
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
00
10
D
00
D
D
10
10
D
+ 1)
00
00
D
Inactive period
(D
10
D
00
00
− D
10
+ 1)
D
D
11
01
D
01
D
D
D
D
11
11
01
11
D
01
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