DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 924

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 26 Electrical Characteristics
(3) Bus Timing
Table 26.50 shows the bus timing. Operation in external expansion mode is not guaranteed when
operating on the subclock ( = 32.768 kHz).
Table 26.50 Bus Timing
Condition A: V
Condition B: V
Condition C: V
Item
Address
delay time
Address
setup time
Address
hold time
CS delay
time (IOS)
AS delay
time
RD delay
time 1
RD delay
time 2
Read data
setup time
Read data
hold time
Rev. 4.00 Sep 27, 2006 page 878 of 1130
REJ09B0327-0400
Symbol Min
t
t
t
t
t
t
t
t
t
AD
AS
AH
CSD
ASD
RSD1
RSD2
RDS
RDH
T
specifications)
T
specifications)
V
T
a
a
a
CC
CC
CC
SS
= –20 to +75°C (regular specifications), T
= –20 to +75°C (regular specifications), T
= –20 to +75°C
= 0 V, = 2 MHz to maximum operating frequency,
= 5.0 V ±10%, V
= 4.0 V to 5.5 V, V
= 2.7 V to 5.5 V (mask ROM version), V
0.5
t
0.5
t
15
0
cyc
cyc
Condition A
–15
–10
20 MHz
Max
20
20
30
30
30
SS
= 0 V, = 2 MHz to maximum operating frequency,
SS
= 0 V, = 2 MHz to maximum operating frequency,
Min
0.5
t
0.5
t
20
0
cyc
cyc
Condition B
–20
–15
16 MHz
Max
30
30
45
45
45
a
a
CC
Min
0.5
t
0.5
t
35
0
= –40 to +85°C (wide-range
= –40 to +85°C (wide-range
cyc
cyc
Condition C
= 3.0 V to 5.5 V (F-ZTAT version),
–30
–20
10 MHz
Max
40
40
60
60
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Conditions
Figure 26.10
to
figure 26.14

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